The disclosed embodiments relate to methods and apparatus for controlling electrolyte hydrodynamics during electroplating. More particularly, methods and apparatus described herein are particularly useful for plating metals onto semiconductor wafer substrates, such as through resist plating of small microbumping features (e.g., copper, nickel, tin and tin alloy solders) having widths less than, e.g., about 50 μm, and copper through silicon via (TSV) features.
Electrochemical deposition processes are well-established in modern integrated circuit fabrication. The transition from aluminum to copper metal line interconnections in the early years of the twenty-first century drove a need for increasingly sophisticated electrodeposition processes and plating tools. Much of the sophistication evolved in response to the need for ever smaller current carrying lines in device metallization layers. These copper lines are formed by electroplating the metal into very thin, high-aspect ratio trenches and vias in a methodology commonly referred to as “damascene” processing (pre-passivation metalization).
Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally and colloquially as wafer level packaging (WLP) and through silicon via (TSV) electrical connection technology. These technologies present their own very significant challenges due in part to the generally larger feature sizes (compared to Front End of Line (FEOL) interconnects) and high aspect ratios.
Depending on the type and application of the packaging features (e.g., through chip connecting TSV, interconnection redistribution wiring, or chip to board or chip bonding, such as flip-chip pillars), plated features are usually, in current technology, greater than about 2 micrometers and are typically about 5-100 micrometers in their principal dimension (for example, copper pillars may be about 50 micrometers). For some on-chip structures such as power busses, the feature to be plated may be larger than 100 micrometers. The aspect ratios of the WLP features are typically about 1:1 (height to width) or lower, though they can range as high as perhaps about 2:1 or so, while TSV structures can have very high aspect ratios (e.g., in the neighborhood of about 20:1).
With the shrinking of WLP structure sizes from 100-200 um to less than 50 um comes a unique set of problems because at this scale, the hydrodynamic and mass transfer boundary layers are nearly equivalent. For prior generations with larger features, the transport of fluid and mass into a feature was carried by the general penetration of the flow fields into the features, but with smaller features, the formation of flow eddies and stagnation can inhibit both the rate and uniformity of mass transport within the growing feature. Therefore, new methods of creating uniform mass transfer within smaller “microbump” and TSV features are required.
Further, the time constant τ (the 1D diffusion equilibration time constant) for a purely diffusion process scales with feature depth L and the diffusion constant D as
  τ  =                    L        2                    2        ⁢        D              ⁢                  (        sec        )            .      
Assuming an average-reasonable value for the diffusion coefficient of a metal ion (e.g., 5×10−6 cm2/sec), a relatively large FEOL 0.3 um deep damascene feature would have a time constant of only about 0.1 msec, but a 50 um deep TSV of WLP bump would have a time constant of several seconds.
Not only feature size, but also plating speed differentiates WLP and TSV applications from damascene applications. For many WLP applications, depending on the metal being plated (e.g., copper, nickel, gold, silver solders, etc.), there is a balance between the manufacturing and cost requirements on the one hand and the technical requirements and technical difficulty on the other hand (e.g., goals of capital productivity with wafer pattern variability and on wafer requirements like within die and within feature targets). For copper, this balance is usually achieved at a rate of at least about 2 micrometers/minute, and typically at least about 3-4 micrometers/minute or more. For tin plating, a plating rate of greater than about 3 um/min, and for some applications at least about 7 micrometers/minute may be required. For nickel and strike gold (e.g., low concentration gold flash film layers), the plating rates may be between about 0.1 to 1 um/min. At these metal-relative higher plating rate regimes, efficient mass transfer of metal ions in the electrolyte to the plating surface is important.
In certain embodiments, plating must be conducted in a highly uniform manner over the entire face of a wafer to achieve good plating uniformity WIthin a Wafer (WIW), WIthin and among all the features of a particular Die (WID), and also WIthin the individual Features themselves (WIF). The high plating rates of WLP and TSV applications present challenges with respect to uniformity of the electrodeposited layer. For various WLP applications, plating must exhibit at most about 5% half range variation radially along the wafer surface (referred to as WIW non-uniformity, measured on a single feature type in a die at multiple locations across the wafer's diameter). A similar equally challenging requirement is the uniform deposition (thickness and shape) of various features of either different sizes (e.g. feature diameters) or feature density (e.g. an isolated or embedded feature in the middle of an array of the chip die). This performance specification is generally referred to as the WID non-uniformity. WID non-uniformity is measured as the local variability (e.g. <5% half range) of the various features types as described above versus the average feature height or other dimension within a given wafer die at that particular die location on the wafer (e.g. at the mid radius, center or edge).
A final challenging requirement is the general control of the within feature shape. Without proper flow and mass transfer convection control, after plating a line or pillar can end up being sloped in either a convex, flat or concave fashion in two or three dimensions (e.g. a saddle or a domed shape), with a flat profile generally, though not always, preferred. While meeting these challenges, WLP applications must compete with conventional, potentially less expensive pick and place serial routing operations. Still further, electrochemical deposition for WLP applications may involve plating various non-copper metals such as solders like lead, tin, tin-silver, and other underbump metallization materials, such as nickel, gold, palladium, and various alloys of these, some of which include copper. Plating of tin-silver near eutectic alloys is an example of a plating technique for an alloy that is plated as a lead free solder alternative to lead-tin eutectic solder.